1. Field of the Invention
This invention relates generally to chemical mechanical polishing apparatus, and more particularly to methods for improved edge performance in chemical mechanical polishing applications via a platen-mounted active retaining ring.
2. Description of the Related Art
In the fabrication of semiconductor devices, there is a need to perform Chemical Mechanical Polishing (CMP) operations, including polishing, buffing and wafer cleaning. Typically, integrated circuit devices are in the form of multi-level structures. At the substrate level, transistor devices having diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define the desired functional device. Patterned conductive layers are insulated from other conductive layers by dielectric materials, such as silicon dioxide. As more metallization levels and associated dielectric layers are formed, the need to planarize the dielectric material increases. Without planarization, fabrication of additional metallization layers becomes substantially more difficult due to the higher variations in the surface topography. In other applications, metallization line patterns are formed in the dielectric material, and then metal CMP operations are performed to remove excess metallization. Further applications include planarization of dielectric films deposited prior to the metallization process, such as dielectrics used for shallow trench isolation or for poly-metal insulation.
In the prior art, CMP systems typically implement belt, orbital, or brush stations in which belts, pads, or brushes are used to scrub, buff, and polish one or both sides of a wafer. Slurry is used to facilitate and enhance the CMP operation. Slurry is most usually introduced onto a moving preparation surface, e.g., belt, pad, brush, and the like, and distributed over the preparation surface as well as the surface of the semiconductor wafer being buffed, polished, or otherwise prepared by the CMP process. The distribution is generally accomplished by a combination of the movement of the preparation surface, the movement of the semiconductor wafer and the friction created between the semiconductor wafer and the preparation surface.
FIG. 1 illustrates an exemplary prior art CMP system 10. The CMP system 10 in FIG. 1 is a belt-type system, so designated because the preparation surface is an endless belt 18 mounted on two drums 24 which drive the belt 18 in a rotational motion as indicated by belt rotation directional arrows 26. A wafer 12 is mounted on a wafer head 14, which is rotated in direction 16. The rotating wafer 12 is then applied against the rotating belt 18 with a force F to accomplish a CMP process. Some CMP processes require significant force F to be applied. A platen 22 is provided to stabilize the belt 18 and to provide a solid surface onto which to apply the wafer 12. Slurry 28 composing of an aqueous solution such as NH4OH or DI containing dispersed abrasive particles is introduced upstream of the wafer 12. The process of scrubbing, buffing and polishing of the surface of the wafer is achieved by using an endless polishing pad glued to belt 18. Typically, the polishing pad is composed of porous or fibrous materials and lacks fixed abrasives.
FIG. 2 is a detailed view of a conventional wafer head and platen configuration 30. The wafer head and platen configuration 30 includes the wafer head 14 and the platen 22 positioned below the wafer head 14. The wafer head 14 includes a fixed retaining ring 32 that holds the wafer 12 in position below the wafer head 14. Between the wafer head 14 and the platen 22 is the polishing pad and belt 18. Often, the platen includes air holes to provide upward air pressure to the polishing pad and belt 18, thus providing a cushion of air upon which to apply the wafer 12.
The CMP process is often used to remove excess film overburden, such as a layer of copper or oxide dielectric. However, the prior art wafer head and platen configuration 30 typically causes a high removal rate along the edges of the wafer 12, and a more moderate removal rate in the interior of the wafer 12, as illustrated in FIGS. 3A and 3B.
FIG. 3A is an illustration showing positional information on the wafer 12. The wafer 12 includes positional designations 40, wherein the center of the wafer is marked as the origin (position 0), the left most edge as position −100 and the right most edge as position 100. Measuring the removal rate of the polished layer on the wafer 12 at each position 40 during a conventional CMP process results in the graph of FIG. 3B.
FIG. 3B is a graph 50 showing the CMP removal rate as a function of wafer position during a conventional CMP operation. As shown by the graph 50, the removal rate at the edge of the wafer is extremely high relative to the removal rate at other positions 40 along the wafer surface. This is a result of the retaining ring 32 interfering with the polishing of the exposed wafer surface, the surface and thickness characteristics of the retaining ring 32 adversely affect the wafer polishing. As a result of the high removal rate at the edge of the wafer surface, the wafer edges may become rounded, which adversely affects the quality of the wafer 12.
In view of the foregoing, there is a need for an improved CMP process that more closely maintains an even removal rate throughout the CMP process. The method should allow for fine tuning of wafer edge removal rates so as to provide an evenly polished wafer surface.